The present invention is an improvement on the electron beam fabrication system described in U.S. Pat. No. 3,679,497, issued July 25, 1972, and assigned to the assignee of the present invention.
The electron beam fabrication system employs a scanning electron microscope to produce a photocathode source or electromask. The photocathode source is adapted to project, on irradiation typically by ultraviolet radiation, an electron beam in the desired pattern which impinges on an electroresist layer on a major surface of a member to implant in said resist layer a differential solubility between the irradiated and the unirradiated areas. Removing the more soluble portions of the electroresist layer after irradiation selectively exposes the underlying member or layer on the member which can in turn be selectively altered through windows in the electroresist of the desired component pattern, typically by etching, diffusion or deposition.
The electromask designates the pattern-bearing photocathode assembly which is analogous to the photomask in the well known photolithographic techniques. The electromask comprises a light transmissive substrate such as quartz on which the photocathode source is supported. The photocathode source is usually adapted to generate the patterned electron beam by overlaying the substrate with a layer such as titanium dioxide which is opaque to the radiation to which the photocathode material is sensitive. The negative of the desired component pattern is formed in the opaque layer and thereafter a contiguous layer of a photocathodic material such as palladium is formed thereover. The patterned electron beam thereafter is generated by irradiating the photocathode layer through the substrate and the opaque layer. See, e.g., U.S. Pat. Nos. 3,585,433, 3,588,570, 3,686,028 and 3,672,987.
The scanning electron microscope of such fabrication system involves the use of a finely focused electron beam to generate a planar component pattern, with submicron accuracy, in an electroresist layer or the like. The electron beam is automatically moved through the pattern matrix on command from a computer. The beam control information can be stored on a magnetic tape which is fed into the computer, which it is used to command the position and movement of the electron beam. Such a scanning electron beam system can be used to directly develop a high resolution pattern in an electroresist in making an integrated circuit.
The main problem in the use of such scanning electron beams is maintaining the accuracy over the entire pattern field. Resolution as such is not a problem in the use of the scanning electron beam. Lines less than 0.5 micron in width can be reliably reproduced in resist materials. However, the pattern field size of integrated circuits are typically as great as 2000 .times. 2000 microns and often as great as 4000 .times. 4000 microns. For electron optical reasons it is impractical to deflect the electron beam through more than a few degrees and still hold the high resolution of, for example, 0.5 micron. It is possible to increase the field size by increasing the distance between the deflecting means and the electroresist, but this correspondingly increases the diameter of the focused electron beam and in turn sacrifices resolution. Thus, for a given resolution, the field size for the scanning electron beam is usually restricted to considerably less than the member size of the integrated circuit. For example, for an electron beam of 0.2 micron in diameter and a resolution of 0.5 micron, the throw of the electron beam is limited to 2 inches and field size is limited to about 2000 microns in diameter.
Another restriction on the size of the field is the accuracy with which the electron beam can be deflected. This depends primarily on the electronics used to control the beam position. At present, the deflection accuracy of an electron beam of 0.2 micron diameter in a 2000 micron field is at best about 0.5 micron. Thus, a typically 2000 .times. 2000 micron field of a scanning electron beam system is divided into 4000 .times. 4000 array of points each 0.5 micron apart; with the 4000 addresses on each axis provided by a 12 bit digital-analog converter. While memories are available with far greater numbers of addresses, larger fields and greater resolution within the same size fields cannot be obtained because of beam deflection limitations.
Ideally the problem can be remedied by sequentially developing the electroresist in multiple patterns of small fields. However, accurate registrations between contiguous fields is essential to the operability of such a technique. The high resolution, e.g. 0.5 micron, of the scanning electron beam system is lost unless the same resolution can be maintained in alignment of the successive patterns. Thus, the electron radiation for each field must be aligned with respect to the adjoining field with a precision of 0.5 micron or less. Otherwise the precisions and economics of the electron beam fabrication system will not be attained in the integrated circuit device.
It has been proposed to simply accurately move the member on which the integrated circuit is to be formed from field to field by mechanical means, using a laser beam to maintain registration, see e.g., U.S. Pat. Nos. 3,632,205 and 3,719,780. However, such a system is not believed commercially practical. A change of only 0.01 percent in the physical alignment of the member can lead to an 0.2 micron error in the registration of adjacent fields. On a 2 .times. 2 inch member such an alignment error results from an 0.002 inch variation in dimension. Further, the deflection aberrations of the electron beam are such that an exactly regular rectangular array of fields is impossible to attain. Even with compensation, distortions remain that add to the mismatch between adjacent fields. Thus, a need exists for a multiple sequential alignment system which will accurately and rapidly register adjacent fields of a desired electroresist pattern.
The need is particularly acute in Large Scale Integration (LSI) technology. LSI is the term applied to integrated circuits which provide high complexity electronic circuits (e.g. more than a thousand gates) in the same semiconductor wafer. Logically LSI technology requires larger and larger wafers; and LSI wafers measuring 2 and 3 inches on a side are now used. However, such large patterns can be generated with a scanning electron microscope only by combining several fields, where accurate registration between fields is essential. Moreover, LSI technology requires a greater density of electronic components and in turn better generation and alignment resolution. The quantative yield of such integration corresponds directly to the size of the wafer. The probability of defects in the single crystal structure increases directly with the volume of the wafer. Thus, the higher the resolution that can be attained, the greater the circuit density that can be utilized, the smaller the wafer size that is needed, the greater the quantative yield of the integration that results.
In the electron image projection system, there is also a need for precision registration and alignment of the patterned electron beam from the photocathode source and the member. The resolution of the electron beam image projection system, e.g., less than 0.5 micron, is lost in a juxtaposition of component patterns unless the same resolution can be maintained in the alignment of successive electromasks. Making of an integrated circuit device requires, for example, registration and irradiation of at least two to ten different juxtapositioned component patterns in electroresist patterns that are subsequently developed and transferred to the component layer by etching, doping or deposition. The electron radiation of each pattern must be aligned with precisely located areas on the major surface of the member each time with a position of 0.5 micron or less with respect to the first pattern. Otherwise, the precision and economies of the electron fabrication system will not be obtained in the finished integrated circuit device.
Apparatus has been developed for precision juxtaposition of multiple component patterns by use of electron beam induced conductivity marks (EBIC), see, e.g., U.S. Pat. No. 3,710,101, granted Jan. 9, 1973 and assigned to the same assignee as the present application. The alignment system comprises at least one and preferably two spaced apart alignment electron beam marks or portions of predetermined cross-sectional shape as part of the photocathode source; and detection marks of predetermined shapes, preferably of the same shape and dimensions as the corresponding alignment beam portions, are formed in an oxide layer on a member and overlaid with a metal layer.
A DC potential is applied across the oxide layer between the metal layer and the member. The subsequent current flow between the terminals will vary in accordance to the portion or area of the detector mark irradiated by the corresponding alignment beam portion. Thus, the alignment beam portion can be precisely aligned with the detector mark by reading the electron induced current corresponding to the area of the detector mark irradiated. Electrical current flow may be processed through an amplifier to actuate a servo-mechanism to move the photocathode source or the substrate, or to change the magnetic field of focusing and deflecting electromagnetic coils surrounding the photocathode source and member to align and direct the electron beam pattern, and in turn provide automatic alignment of the alignment beam portions and corresponding detector marks.
High precision in positioning the electron beam pattern is possible with this alignment system by making the alignment beam portion of the photocathode source and the detector marks of the same dimensions and relative spacings. Such alignment system is capable of automatically positioning both alignment bean portions on their corresponding detector marks to an error of about .+-.0.1 micron within a few seconds. The performance of such alignment beam system is therefore completely adequate to provide the necessary accuracy and speed of alignment.
However, the difficulty with this alignment system is that the detector marks must be fabricated on the member itself. Although this can be accomplished in some instances with negligible interference, it may require additional fabrication steps to prepare the detector marks on the member for the alignment system. Specifically, before alignment and exposure of each successive pattern, the electroresist layer must be removed from the area adjacent to the detector marks and a metal layer evaporated over such area to fabricate the detector mark.
Further, steps must be taken during the processing to ensure preservation of the alignment marks in the insulator layer through the various processing steps involved in fabrication of the integrated circuit. For example, where an epitaxial growth is required, the detector mark areas must be masked to ensure that growth does not occur over the insulator layer and obliterate the alignment detector mark. Alternatively, precautions must be exercised through the various processing steps such as diffusion, oxidation, depositions, etc. to ensure in particular that sufficient contrast is maintained between the thick and thin portions of the insulator layer which define the detector marks.
Moreover, the alignment system requires providing a circuit across the detector marks which is expensive and cumbersome; remote readings from the detector marks cannot be made.